Copyright © Future Technology Devices International Limited

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FT600Q-FT601Q IC DatasheetDatasheet

Version 1.04

Document No.: FT_001118

Clearance No.: FTDI#424

Appendix B – List of Figures and Tables

List of Figures

Figure 2.1 Block Diagram..............................................................................................................3

Figure 3.1 QFN56 Package Pin Out ..................................................................................................6

Figure 3.2 QFN76 Package Pin Out ..................................................................................................7

Figure 4.1 FT601 Multi-Channel FIFO mode master read transaction 1 .............................................. 14

Figure 4.2 FT601 Multi-Channel FIFO mode master read transaction 2 .............................................. 14

Figure 4.3 FT601 Multi-Channel FIFO mode master write transaction 1.............................................. 15

Figure 4.4 Multi-Channel FIFO mode master write transaction 2 ....................................................... 16

Figure 4.5 Multi-Channel FIFO mode master read followed by write transaction .................................. 16

Figure 4.6 245 Synchronous FIFO mode bus master read cycle ........................................................ 17

Figure 4.7 245 Synchronous FIFO mode bus master write cycle........................................................ 17

Figure 4.8 FIFO Bus AC timing diagram ......................................................................................... 18

Figure 6.1 Bus-Powered Configuration-3.3V I/O.............................................................................. 22

Figure 6.2 Bus-Powered Configuration-2.5V/1.8V I/O ...................................................................... 22

Figure 6.3 Self-Powered Configuration........................................................................................... 23

Figure 7.1 FT600/FT601 Connect to FIFO Master Interface (Multi-Channel FIFO Mode) ........................ 24

Figure 7.2 FT600/FT601 Connect to FIFO Master Interface (245 Synchronous FIFO Mode) ................... 24

Figure 8.1 QFN-56 Package Dimensions........................................................................................ 25

Figure 8.2 QFN-56 Package Markings ........................................................................................... 26

Figure 8.3 QFN-76 Package Dimensions........................................................................................ 27

Figure 8.4 QFN-76 Package Markings ........................................................................................... 28

List of Tables

Table 1.1 Device Part Numbers.......................................................................................................2

Table 3.1 Device pin out Signal descriptions................................................................................... 10

Table 4.1 Multi-Channel FIFO mode Command phase ...................................................................... 13

Table 4.2 FIFO Bus AC timing....................................................................................................... 18

Table 5.1 Absolute Maximum Ratings ............................................................................................ 19

Table 5.2 ESD and Latch-Up Specifications .................................................................................... 19

Table 5.3 DC Characteristics ........................................................................................................ 20

Table 5.4 DC Characteristics for I/O Interface (Except USB PHY pins)................................................ 21