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FT600Q-FT601Q IC DatasheetDatasheet

Version 1.04

Document No.: FT_001118

Clearance No.: FTDI#424

BE[3:0](BE[1:0] for FT600) is byte enable signal. In bus master read operation, the FT60X asserts the

signal for the valid bytes in a word strobe. In bus master write operation, the bus master assets the

signal for the valid bytes in a word strobe. Normally, all 4 bytes should be valid in a bus transaction

except in the last word strobe when the data transaction length not aligned at word boundary.

There are 2 waveforms below to show 245 synchronous FIFO bus master write and read cycles.

Figure 4.6 245 Synchronous FIFO mode bus master read cycle

⃰In 245 Synchronous FIFO mode master read operation, the bus master shall be able to read out the

maximum possible data in the RX FIFO in one read transaction, i.e. the bus master shall be able to read

out 4 KB in one bus transaction. In write operations, if the bus master expects the data to be transferred

on the USB bus in a maximum possible packet length, it should write the data to the FIFO in a single bus

transaction.

E.g. in a USB 3.0 super-speed connection, with a packet size of 1 KB, and a FIFO size of 4 KB, if the bus

master completes the 4 KB in one transaction then the data will be transferred over the USB bus in 4 full

sized packets. If the bus master completes 1 KB in one transaction, the data will be transferred over the

USB bus in 1 packet. If the bus master completes 1025 bytes in one transaction, the data will be transferred

over USB in 1 full sized packet and one short packet with 1 byte.

Figure 4.7 245 Synchronous FIFO mode bus master write cycle