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AM263P4 数据表(PDF) 116 Page - Texas Instruments |
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AM263P4 数据表(HTML) 116 Page - Texas Instruments |
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116 / 168 page  NO. PARAMETER DESCRIPTION MIN MAX UNIT SM9 td(SPICLK-CS) Delay time, spi_sclk last edge to spi_cs[x] inactive PHA = 0 –4 + A(2) ns PHA = 1 –4 + B(3) ns (1) P = SPICLK period in ns. (2) When P = 20.8ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. (3) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2. SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM8 SM9 SM6 SM3 SM1 SM2 SM1 SM8 SM9 SM3 SM1 SM2 SM1 SM6 SM7 SM6 SM2 SM3 SM2 SM3 SM6 SM6 SM6 SPRSP08_TIMING_McSPI_01 Figure 6-25. SPI Controller Mode Transmit Timing 6.11.5.10.4 SPI Peripheral Mode Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT SS1 tc(SPICLK) Cycle time, spi_sclk 40 ns SS2 tw(SPICLKL) Typical Pulse duration, spi_sclk low 0.45 × P(1) ns SS3 tw(SPICLKH) Typical Pulse duration, spi_sclk high 0.45 × P(1) ns SS4 tsu(SIMO-SPICLK) Setup time, spi_d[x] valid before spi_sclk active edge 5 ns SS5 th(SPICLK-SIMO) Hold time, spi_d[x] valid after spi_sclk active edge 5 ns AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1 SPRSP81D – OCTOBER 2023 – REVISED MAY 2025 www.ti.com 116 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 |
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