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AM263P4 数据表(PDF) 117 Page - Texas Instruments |
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AM263P4 数据表(HTML) 117 Page - Texas Instruments |
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117 / 168 page  NO. PARAMETER DESCRIPTION MIN MAX UNIT SS8 tsu(CS-SPICLK) Setup time, spi_cs[x] valid before spi_sclk first edge 5 ns SS9 th(SPICLK-CS) Hold time, spi_cs[x] valid after spi_sclk last edge 5 ns (1) P = SPICLK period. SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS8 SS9 SS8 SS9 SS2 SS3 SS2 SS2 SS4 SS5 SS5 SS4 SS4 SS5 SS4 SS5 SPRSP08_TIMING_McSPI_04 Figure 6-26. SPI Peripheral Mode Receive Timing 6.11.5.10.5 SPI Peripheral Mode Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT Normal Mode SS6 td(SPICLK-SOMI) Delay time, spi_sclk active edge to mcspi_somi transition 2 17.12 ns SS7 tsk(CS-SOMI) Delay time, spi_cs[x] active edge to mcspi_somi transition 20.95 ns www.ti.com AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1 SPRSP81D – OCTOBER 2023 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 |
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