AM263P4 datasheet(123/168 Pages) TI2

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Implementing data training enables proper operation across temperature with a specific process, voltage, and

frequency operating condition, while achieving a higher operating frequency.

Data transmit and receive timing parameters are not defined for the data training use case since they are

dynamically adjusted based on the operating condition.

6.11.5.12.2.1.1 OSPI DLL Delay Mapping for PHY Data Training

MODE

OSPI_PHY_CONFIGURATION_REG BIT

FIELD

DELAY VALUE

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD

(1)

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

(2)

(1)

Transmit DLL delay value determined by training software

(2)

Receive DLL delay value determined by training software

6.11.5.12.2.1.2 OSPI Timing Requirements - PHY Data Training

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid

before active OSPI0_DQS edge

DDR with DQS

(1)

O16

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid

after active OSPI0_DQS edge

DDR with DQS

(1)

Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum

data valid window.

tO16t

O15

OSPI_DQS

OSPI_D[i:0]

Figure 6-32. . OSPI0 Timing Requirements – PHY Data Training, DDR with DQS

6.11.5.12.2.1.3 OSPI Switching Characteristics - PHY Data Training

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

3.3V, DDR

7.52

tw(CLKL)

Pulse duration, OSPI0_CLK low

DDR

0.475P(1) - 0.3

tw(CLKH)

Pulse duration, OSPI0_CLK high

DDR

0.475P(1) - 0.3

td(CSn-CLK)

Delay time, OSPI0_CSn[1:0] active edge

to OSPI0_CLK rising edge

DDR

0.475P(1) + (0.975

× M(2) × R(4)) +

0.65TD(5) - 1

0.525P(1) + (1.025

× M(2) × R(4)) +

0.175TD(5) + 1

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[1:0] inactive edge

DDR

0.475P(1) + (0.975

× N(3) × R(4)) -

0.065TD(5) - 1

0.525P(1) + (1.025

× N(3) × R(4)) -

0.175TD(5) + 1

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

DDR

(6)

(1)

P = OSPI0_CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = REFCLK cycle time in ns

(5)

TD = PHY_CONFIG_TX_DLL_DELAY_FLD

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AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1

SPRSP81D – OCTOBER 2023 – REVISED MAY 2025

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