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AM263P4 数据表(PDF) 124 Page - Texas Instruments |
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AM263P4 数据表(HTML) 124 Page - Texas Instruments |
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124 / 168 page  (6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data valid window. tO4t tO3t tO5t tO2t tO1t O6 O6 OSPI_CSn OSPI_CLK OSPI_D[i:0] Figure 6-33. OSPI0 Switching Characteristics – PHY DDR Data Training 6.11.5.12.2.2 OSPI0 Without Data Training Note Timing parameters defined in this section are only applicable when data training is not implemented and DLL delays are configured as described in OSPI DLL Delay Mapping for PHY SDR Timing Modes and OSPI DLL Delay Mapping for PHY DDR Timing Modes. 6.11.5.12.2.2.1 OSPI0 PHY SDR Timing 6.11.5.12.2.2.1.1 OSPI DLL Delay Mapping for PHY SDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE Transmit All Modes PHY_CONFIG_TX_DLL_DELAY_FLD 0x23 Receive SDR with Internal PHY Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0x2D SDR with External Board Loopback PHY_CONFIG_RX_DLL_DELAY_FLD 0xA 6.11.5.12.2.2.1.2 OSPI Timing Requirements - PHY SDR Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge 3.3V, SDR with Internal PHY Loopback 7 ns O20 th(CLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge 3.3V, SDR with Internal PHY Loopback 0 ns O21 tsu(D-LBCLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge 3.3V, SDR with External Board Loopback 7 ns O22 th(LBCLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge 3.3V, SDR with External Board Loopback 4.7 ns AM263P4, AM263P2, AM263P4-Q1, AM263P2-Q1 SPRSP81D – OCTOBER 2023 – REVISED MAY 2025 www.ti.com 124 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM263P4 AM263P2 AM263P4-Q1 AM263P2-Q1 |
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