L5965 datasheet(18/73 Pages) STMICROELECTRONICS

18 / 73 page

4.2

Voltage regulators and features description

4.2.1

VREG

VREG is an internal regulator used to supply Buck1, Buck3 and Buck4. Its output (6.0 V typical) is available at

VREG pin and decoupled by using a ceramic capacitor (2.2 µF suggested). The regulator has an internal current

limitation protection.

An external supply can be provided at EXTSUP pin, in parallel to VBAT1. In ACTIVE mode, if EXTSUP is higher

than a fixed threshold (typically 4.6 V), VREG supply is automatically switched to EXTSUP. It helps to improve

efficiency and save power dissipation when VBAT1 is higher than EXTSUP.

In case of over-temperature detection on VREG, the PMIC enters REC mode.

When the PMIC is in RAMPUP MAIN or SECUP mode, in case of fail of “vreg ok" on VREG, the IC enters REC

mode.

When the PMIC is in other modes, in case of fail of “vreg ok" on VREG, the IC provides a "vreg not ok" status via

SPI bit and asserts the FAULT pin.

VREG output value influences the PMIC power-up phase when BUCK2 is configured as main buck.

The minimum value of VBAT1 required to switch-on the IC can be calculated as Vth(VREG_OK)_rising + VREG

drop.

In RAMPUP MAIN and SECUP modes, if VBAT1 has not reached the minimum required value and VREG is not

ok, then FSM moves to REC state.

In ACTIVE mode, if VBAT1 has not reached the minimum required value and VREG is not ok, all related analog

blocks (buck1, buck3, buck4) are active, but the SPI bit and FAULT pin are asserted. To make sure that BUCK1,

BUCK3 and BUCK4 fully work, VREG should be higher than 3.5 V.

If this regulator is disabled and not used, EXSUP pin should be connected to ground.

Figure 8. VREG influence on PMIC behavior

SHUTDOWN

RAMPUP

…...

VREG

FSM

ACTIVE

…...

FAULT pin

Vreg_ok

Vth(vreg_ok)_fall

Vreg=6V

VBAT1

Vth(POR)_rise

Vth(vreg_ok)_rise+vreg drop

Vth(vreg_ok)_rise

Vreg_drop

VBAT1(min)

GADG2711180930PS

4.2.2

Pre regulator BUCK1

BUCK1 controller operates using constant frequency peak current mode control. According to OTP selection, it

can work as Main BUCK pre-regulator (enabled by WKUP pin signal) or as post-regulator. The input voltage

(VBAT1) is compatible to battery level and the overvoltage detection of VBAT1 (typ 32 V, available via SPI and

enabled by default) can be disabled via SPI (enabled by default). The switching frequency is set to 400 kHz with

the possibility to have Spread Spectrum (enabled by default and disabled via SPI). Driving stage maximum output

current is programmable via SPI to 1 A or 2 A. Output voltage is programmable via OTP to 8 possible values

(5.0 V, 3.8 V, 3.3 V, 1.8 V, 1.2 V, 1.1 V, 1.0 V or 0.8 V). The inductor current is monitored by a Sense Amplifier,

sensing the drop on an external resistor, then the current limit value depends on the resistor value. Output power

stage dead time (to avoid Cross Conduction) is programmable via SPI on 8 different levels. Soft Start time is

programmable via SPI. Compensation network is external.

L5965

Voltage regulators and features description

DS12567 - Rev 3

page 18/73

L5965 数据表(PDF) 18 Page - STMicroelectronics

L5965 数据表(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

数据表下载