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L5965 数据表(PDF) 25 Page - STMicroelectronics |
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L5965 数据表(HTML) 25 Page - STMicroelectronics |
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25 / 73 page  4.2.12 Reset and Fault In ACTIVE mode, a reset signal is generated by L5965 at RESET_B pin in case of UV, OV if enabled by OTP, PG loss on Main regulator and Watchdog failure (wrong trigger of WD). Every regulator that can issue a reset, moves the device to REC state. Reset behavior at Power Up phase is fully described in Section 6 Device operating mode. Figure 12. Reset circuit diagram in ACTIVE mode GAPG2306150942PS ≥ 1 RESET_B pin Watchdog failure (main) Buck1/2_pg_loss (main) Buck1/2_mon_uv Ldo_mon_uv/ov Buck4_pg_loss Buck4_mon_uv/ov Buck3_pg_loss Buck3_mon_uv/ov SPI control bits OTP user setup & (post) Buck1/2_pg_loss (post) Buck1/2_mon_uv/ov (post) Buck1/2_mon_uv MUX A loss of ground (PGLOSS) asserts RESET_B with the following rules: 1. if the regulator is disabled by OTP, PGLOSS cannot assert RESET_B; 2. if the regulator is enabled by OTP, but it is not in the Reset Activation list, PGLOSS cannot assert RESET_B; 3. if the regulator is enabled by OTP and it is in the Reset Activation list, no matter if it is disabled by SPI, PGLOSS can assert RESET_B. The undervoltage (UV) asserts RESET_B with the following rules: • if the regulator is disabled by OTP, UV cannot assert RESET_B; • if the regulator is enabled by OTP, but it is not in the Reset Activation list, UV cannot assert RESET_B; • it the regulator is enabled by OTP and it is in the Reset Activation list, but it is disabled by SPI, UV cannot assert RESET_B; • if the regulator is enabled by OTP, it is in the Reset Activation list and it is not disabled by SPI, UV can assert RESET_B. The overvoltage (OV) asserts RESET_B in a similar way as the undervoltage, with this additional condition: • if OvRst_EN is set to 0 through OTP, the OV cannot assert RESET_B. A FAULT signal is generated in active mode in case of a fault, as shown in Figure 13. • "SPI_parity_fail" refers to SPI_PAR_FAIL, Bit2 of SPI fault STAT • "PowerUp fault" is an error generated by regulators during power-up phase: – each regulator should complete its own power-up phase up to the power good signal within 20 ms • "LBIST_err" is an error generated by one of the following checks: – Buck clock generation – Logic diagnostics circuit – Main State Machine L5965 Voltage regulators and features description DS12567 - Rev 3 page 25/73 |
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