L5965 datasheet(32/73 Pages) STMICROELECTRONICS

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SPI format and register mapping

A 32-bit SPI bus is used for bi-directional communication with the microcontroller, for functional and test purpose.

A write operation leads to a modification of the addressed data by the payload if a write access is allowed (e.g.

control register, valid data). A read operation (based on previous communication request) shifts out the data

present in the addressed register (out of frame data exchange protocol). MISO (multi-slave) operation is not

supported.

A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by

payload bits set to 0. The SPI word is represented in the below figure.

Figure 20. SPI word representation

SPI

ERR

Bit

IERR

29 28 27

ADDRESS

26 25

ADDRESS FBACK

24 23 22

RSV

CNT

20 19 18 17 16 15 14 13

DATA WRITE

DATA READ

12 11 10

CRC

GAPG2306150958PS

In REC mode, SPI registers are NOT reset. Only SPI_WDI is reset but in INIT mode or power_down (when in

POR).

Logic content is reset only by POR activation, once VBAT falls below POR threshold. WD_TWIN is not reset by a

Reset command (or a WD fail) regardless of ‘WD_REC_en’ value.

DI Stream:

•

Bit 31: R/W flag. To select read (0) or write (1) operation

•

Bit 30-23: SPI register address

•

Bit 22: Test Mode flag

•

Bit 21: Frame counter (0/1). After Power-on reset, this bit must be ‘0’. The bit must be toggled according to

the previous SPI CNT bit.

•

Bit 20-5: Data to be written at selected address

•

Bit 4-0: CRC code

DO Stream:

•

Bit 31: Previous SPI communication Error (CRC error, Too long frame, Too short frame, frame count error,

SPI error, CSN low time out)(*)

•

Bit 30:RSTB(*)

•

Bit 29: FAULT(*)

•

Bit 28:21: SPI register address (related to the previous transmission)

•

Bit 20-5: Data read at selected address (related to previous transmission)

•

Bit 4-0: CRC code

Note:

(*) bit 29 and bit 30 reflect the current status of RSTB pin and FAULT pin. Every time the relevant SPI register is

accessed, an internal register will sample the current status of RSTB and FAULT pins, store them, then shift

them out on SPI DO frame at next SPI access. If RSTB and Fault bits in ACTIVE mode are `1' , it means there's

no reset and no fault.

L5965

SPI format and register mapping

DS12567 - Rev 3

page 32/73

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