L5965 datasheet(21/73 Pages) STMICROELECTRONICS

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•

Monitor of the Power Good thresholds: are set via SPI (at 5/10% of VBUCK3) and the status is provided via

SPI bit.

•

Over Current Protection on High Side FET.

•

Over Temperature detection by a local thermal sensor.

•

PGND3 loss detection.

BUCK3 fault management:

•

If a UV/OV fault occurs then the FAULT pin is asserted and the corresponding fault bit is set inside the SPI

activation and power up sequence. In case of OV, it is possible to enable or disable the reset for all

regulators together by OTP. The reset moves the device to REC state.

•

If OT occurs, the power stage is switched OFF with a 16us filter time. The output decreases until UV is

detected. The regulator goes in REC state and can restart only when OT flag is reset. The corresponding

SPI bit is set and FAULT pin is asserted.

•

The over current limitation is a cycle by cycle protection: when the fault happens, the corresponding fault

bit (Buck_OC_STAT) is set in the SPI register. This bit doesn't change the regulator behavior. If the fault

happens for 7 consequent cycles, the FAULT pin is asserted (latched).

•

If PGND3 ground loss occurs, the regulator is turned OFF and the FAULT pin is asserted. RESET_B is

asserted according to OTP reset activation and power up sequence. The device moves to REC state. Until

the fault is present and stored any tentative of turning on the regulator is ignored. BUCK3 can be turned on

again after the fault removal and a Read & Clear cycle.

If this regulator is disabled and not used, VREG3_S and PGND3 pins should be connected to ground.

4.2.5

Post regulator BUCK4

BUCK4 regulator operates using constant frequency peak current mode control. The input voltage (VIN4) is

compatible to the Main regulator output up to 5.5 V. The switching frequency is 2.4 MHz with the possibility to

have Spread Spectrum (enabled by default and disabled via SPI); a phase shift of 270 ° versus BUCK1 is

internally generated. Output voltage is programmable with internal OTP cells to 8 possible values (3.3 V, 1.8 V,

1.35 V, 1.3 V, 1.25 V, 1.2 V, 1.12 V or 1.1 V). The soft start time can be set via SPI. Compensation network is

internal.

BUCK4 regulator provides the following diagnostic:

•

Monitor of the output voltage by an independent circuit for UV/OV detection: thresholds are set via SPI.

•

Monitor of the Power Good thresholds: are set via SPI (at 5/10% of VBUCK4) and the status is provided via

SPI bit.

•

Over Current Protection on High Side FET.

•

Over Temperature detection by a local Thermal sensor.

•

PGND4 loss detection.

BUCK4 Fault management:

•

If a UV/OV fault occurs then the FAULT pin is asserted and the corresponding fault bit is set inside the SPI

activation and power up sequence. In case of OV, it is possible to enable or disable the reset for all

regulators together by OTP. The reset moves the device to REC state.

•

If OT occurs, the power stage is switched OFF with a 16 µs filter time. The output decreases until UV is

detected. The regulator goes in REC state and can restart only when OT flag is reset. The corresponding

SPI bit is set and FAULT pin is asserted.

•

The over current limitation is a cycle by cycle protection: when the fault happens, the corresponding fault

bit (Buck_OC_STAT) is set in the SPI register. This bit doesn't change the regulator behavior. If the fault

happens for 7 consequent cycles, the FAULT pin is asserted (latched).

•

If PGND4 ground loss occurs, the regulator is turned OFF and the FAULT pin is asserted. RESET_B is

asserted according to OTP reset activation and power up sequence. The device moves to REC state. Until

the fault is present and stored any tentative of turning on the regulator is ignored. BUCK4 can be turned on

again after the fault removal, Read & Clear cycle.

If this regulator is disabled and not used, VREG4_S and PGND4 pins should be connected to ground.

L5965

Voltage regulators and features description

DS12567 - Rev 3

page 21/73

L5965 数据表(PDF) 21 Page - STMicroelectronics

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