L5965 datasheet(34/73 Pages) STMICROELECTRONICS

34 / 73 page

Table 9. Input CLK, DI

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Vin L

Input low level

–

Vin H

Input high level

–

2.3

–

Vin Hyst

Input hysteresis

–

0.2

0.4

–

I in

Pull down current at input

Vin = 1.5 V

µ A

Cin

Input capacitance at input pins CSN, CLK, DI

Guaranteed by design

–

fCLK

SPI input frequency at CLK

–

MHz

Table 10. DI, CLK and CSN timing

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tCLK

Clock period

–

1000

–

tCLKH

Clock high time

–

400

–

tCLKL

Clock low time

–

400

–

tset CSN

CSN setup time, CSN low before rising edge of CLK

–

500

–

tset CLK

CLK setup time, CLK high before rising edge of CSN

–

500

–

tset DI

DI setup time

–

thold DI

DI hold time

–

tr in

Rise time of input signal

–

DI, CLK, CSN

tf in

Fall time of input signal

–

DI, CLK, CSN

Table 11. Output DO

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VDOL

Output low level

IDO = -4 mA

–

0.3

IDOLK

Open Drain leakage current

When DO output=high

-5

–

µA

CDO

Open Drain input capacitance

Guaranteed by design

–

Table 12. CSN timing

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tCSN_HI,min

Minimum CSN high time

Transfer of SPI-command to Input Register

–

µs

Active mode

tCSNfail

CSN low timeout

–

5.1

SPI frame CRC generator

The SPI protocol is defined by frames of 32 bits with 5 bits of CRC (Cyclic Redundancy Check) in both input and

output directions. The polynomial calculation implemented is:

g(x)= x^5 + x^2 + 1

the structure of CRC generator is shown in Figure 23. Structure of CRC generator.

Here are the rules:

L5965

SPI frame CRC generator

DS12567 - Rev 3

page 34/73

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