L5965 datasheet(33/73 Pages) STMICROELECTRONICS

33 / 73 page

Figure 21. SPI diagram

CSN

shift

sample

data shifted out

data updated

CLK

GAPG2306151214PS

DO is sampled by the microcontroller on CLK falling edge, DI is sampled by L5965 on CLK falling edge. In case of

writing operation selected, internal register is updated at CSN rising edge.

In the below figure SPI protocol is shown:

•

1st Frame: Write Access on RW Register X → Register X is updated at the end of the frame.

•

After the update of register X, the data out shift register is updated too.

•

2nd Frame: Read Access → Register X with data Y is shifted out on MISO.

•

The data out shift register is updated with the same data.

Figure 22. SPI protocol diagram

CSN

R/W = 1

R/W = 0

Write register X, data Y

Data out to be shifted out updated

CLK

GAPG2306151521PS

CSN

CLK

To detect frame losses/non-refreshment, Bit21 of DI frame must have opposite values in sequential frames. If a

static fault (stuck-at) or cross-talk occurs, the communication data received would not pass the CRC check and

will be discarded: FAULT pin is asserted.

If SPI communication has some errors (no matter to which register), the write in data is discarded. In the next SPI

communication, DO will automatically read out 0x1D register address and data-in order to give details on SPI

error.

Table 8. Input CSN

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VCSNLOW

Input voltage low level

Normal mode

–

VCSNHIGH

Input voltage high level

Normal mode

2.3

–

VCSNHYS

VCSNHIGH - VCSNLOW

Normal mode

0.2

0.4

–

ICSNPU

Internal pull up resistor

Normal mode

–

800

–

kΩ

L5965

SPI format and register mapping

DS12567 - Rev 3

page 33/73

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