L99ASC03 datasheet(46/73 Pages) STMICROELECTRONICS

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ST-SPI Protocol

L99ASC03

46/73

DocID023504 Rev 7

ST-SPI Protocol

4.1

Physical layer

Table 30. SPI pin description

4.1.1

Signal description

Chip Select Not (CSN)

The communication interface is deselected, when this input signal is logically high. A falling

edge on CSN enables and starts the communication while a rising edge finishes the

communication and the sent command is executed when a valid frame was sent. During

communication start and stop the Serial Clock (SCK) has to be logically low. The Serial Data

Out (SDO) is in high impedance when CSN is high or a communication timeout was

detected.

Serial Clock (SCK)

This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is latched on

the rising edge of Serial Clock (SCK) into the internal shift registers while on the falling edge

data from the internal shift registers are shifted out to Serial Data Out (SDO).

Serial Data Input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising edge

of Serial Clock (SCK).

Serial Data Output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (SCK).

4.1.2

Clock and data characteristics

A microcontroller with its SPI peripheral running in following mode can driven ST-SPI:

CPOL = 0 and CPHA = 0.

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