L99ASC03 datasheet(11/73 Pages) STMICROELECTRONICS

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L99ASC03

Device description

stable for output capacitor greater/eqaul than 660 nF (ESR < 50 m

Ω) close to the device. An

additional external capacitor up to 47 µF is permitted.

In case of a short circuit to GND on VDD when VDD is turned on (VDD < VDDFAIL for at least

4 ms), the device automatically enters the VBAT Standby Mode and the VDDFAIL flag is set.

Reactivation of the device is possible through a wake-up event. The VDDFAIL flag can be

cleared by an SPI “Read & Clear” command, once the short circuit is removed and the

device leaves the VBAT Standby Mode.

2.3

NRES reset output

In case the VDD regulator is turned on and its output voltage rises above the VDD reset

threshold, the reset pin NRES is pulled up to VDD by an internal pull-up resistor after a delay

equal to tRP (typ. 2 ms).

A reset pulse is generated if:

•

VDD drops below the VDD reset threshold (VRT1 or VRT2, configurable by SPI through

the VDD_VTH bit). In this case, the VDDUV flag is also set and can be cleared by an SPI

"Read & Clear" command, once the VDD rises back above the programmed VDD_UV

threshold.

•

a watchdog failure occurs.

Figure 3. Supply voltage operation summary

L99ASC03 数据表(PDF) 11 Page - STMicroelectronics