L99ASC03 datasheet(12/73 Pages) STMICROELECTRONICS

12 / 73 page

Device description

L99ASC03

12/73

DocID023504 Rev 7

2.4

Watchdog

A window watchdog is integrated in the device. The watchdog supervises the operation of

the external microcontroller in Active Mode and, if the ICMP bit is set to ‘0’ and IVDD > ICMP,

also in VDD Standby Mode.

When the device powers up and the NRES pin is released, the watchdog is started with a

long open window (typ. 65 ms). The microcontroller has to write the WDTRIG bit to ‘1’ within

this time in order to terminate the long open window and start the window watchdog. After

that, the watchdog has to be serviced properly by alternating the logic value written to the

WDTRIG bit within the watchdog open window. A correct watchdog trigger immediately

starts the next cycle.

After eight consecutive watchdog failures, the VDD regulator is turned off for a time equal to

tVDDoff (typ. 200 ms). In case seven additional and consecutive watchdog failures occur, the

VDD regulator is completely turned off and the device enters VBAT Standby Mode.

A watchdog failure causes a reset pulse at the NRES pin and the deactivation of the gate

drivers (fail-safe condition, for further details see Table 5).

When the device is in Flash Mode, the watchdog is disabled. Besides even in VDD Standby

Mode with ICMP = 1 the WDG is always disabled. If the WDDIS bit is set to ‘1’ in Flash Mode

and then a transition to Active Mode occurs, the watchdog remains disabled in Active Mode

until the next POR.

After a WDG failure event, after a VDD_UV event or after a wake event from VBAT Standby

Mode the watchdog starts again in LOW mode. Once properly toggled the WDGTRIG bit,

writing the same WDGTRIG bit value anywhere within the WDG window does not generate

any WDG failure event.

Figure 4. Watchdog in normal operation mode (part 1)

L99ASC03 数据表(PDF) 12 Page - STMicroelectronics