L99ASC03 datasheet(24/73 Pages) STMICROELECTRONICS

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Device description

L99ASC03

24/73

DocID023504 Rev 7

2.15.2

BEMF comparator sampling

In order to avoid unwanted commutations of the BEMF comparator due to PWM switching

and spurious noise on the motor phases, an intelligent sampling mechanism is implemented

to detect the BEMF zero-crossing point. Depending on the BEMFSW bit (PWM switching

mode), BEMFMOD bit (comparator selection) and BEMFPOL bit, it is possible to select the

triggering instant used to sample and latch the output of the selected BEMF comparator,

which is in turn made available at the BEMFOUT pin. The following cases are possible:

•

PWM on high-side MOSFET

–

BEMF detection in PWM ON state, BEMF sampling on PWM switch turn-off

–

BEMF detection in PWM OFF state, BEMF sampling on PWM switch turn-on or

complementary PWM switch turn-off

•

PWM on low-side MOSFET

–

BEMF detection in PWM ON state, BEMF sampling on PWM switch turn-off

–

BEMF detection in PWM OFF state, BEMF sampling on PWM switch turn-on or

complementary PWM switch turn-off

It is worth noting that this method allows having a stabilized BEMF signal at the motor phase

before the phase voltage can change, thanks to the turn-on and turn-off delay associated to

the gate driver and the external MOSFET.

If no PWM is applied to the motor (100% duty cycle), the output of the BEMF comparator

can be sampled by using an internal clock edge. In this case, the BEMFBY bit has to be set.

2.15.3

BEMF commutation driving mode

The BEMFCNT bits are used to set the motor phase to be monitored by the BEMF

comparator. According to BEMFCM bit value, BEMFCNT bits can be either programmed

through SPI by the system microcontroller or automatically updated by L99ASC03.

In particular:

•

If BEMFCM = '0', the external microcontroller is intended to update BEMFCNT bits

through SPI command every time the BEMF comparator has to monitor another motor

phase.

•

If BEMFCM = '1', the BMFCNT bits are automatically increased (if BEMFDIR = '0') or

decreased (if BEMFDIR = '1') whenever the L99ASC03 receives a triggering pulse on

BC pin. In order to properly operates, triggering pulse amplitude on BC pin must be

coherent with Vin H (see Table 24) electrical parameter.

2.16

Digital multiplexer (DOUT)

An integrated digital multiplexer provides a digital signal on the DOUT pin. Depending on

the setting of the DMUX bit and of the OCFT_DIS bit, it is possible to select between a fail-

safe flag signal, a CSA overcurrent flag signal or the overcurrent comparator output.

2.17

Analog multiplexer (AOUT)

By setting the AMUX bits via SPI, an integrated analog multiplexer provides an output

voltage proportional to the input supply voltages (VS, VSREG or VSMS), to the internal chip

temperature Tj or to the CSA reference voltage.

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