L99ASC03 datasheet(63/73 Pages) STMICROELECTRONICS

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L99ASC03

ST-SPI Protocol

After a device state transition to Active mode or Flash mode, the DEVST bits always report

the previous device state. If an SPI "Read & Clear" command is performed on these bits,

they will then report the current device state.

4.4.11

Device Status Registers 2

Address:

0x12

Type:

R/C

[3] WAKESPI: wake-up from SPI detected

[2] Reserved

[1:0] DEVST: device status

00: Active mode

01: VDD standby mode

10: VBAT standby mode/ POR

11: Flash mode

SPI_DI

Reserved

INHST

VRT2LOW

VDDUV

VDDFAIL

GSB reported

—

Information

Clear mode

Read & Clear

—

Information

Read & Clear

Bit Bit description

[7] SPI_DI: short circuit on SDI pin detected (all 0's or all 1's detected on SDI pin)

[6] Reserved

[5] Reserved

[4] Reserved

[3] INHST: INH pin status (0: logic LOW; 1: logic HIGH)

[2] VRT2LOW: VDD detected to be below the VRT2 threshold, in case the VRT1 reset threshold is

selected (VDD_VTH = 0).

[1] VDDUV: VDD undervoltage detected

[0] VDDFAIL: VDD FAIL detected

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