L99ASC03 datasheet(54/73 Pages) STMICROELECTRONICS

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ST-SPI Protocol

L99ASC03

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DocID023504 Rev 7

4.4.2

Device Control Register 1

Address:

0x1

Type:

R/W

Description:

In this register, device operating information is stored. This register is not set to

default in case of fail-safe errors.

Bit name

WDDIS

CPDIS

TEMPM

ICMP

VDD_VTH

STBYSEL

GOSTBY

WDTRIG

Default values

Bit Bit description

[7] WDDIS: WatchDog DISable (writable in FLASH mode only)

0: window watchdog enabled

1: window watchdog disabled

[6] CPDIS: Charge Pump DISable

0: charge pump enabled

1: charge pump disabled

[5] TEMPM: TEMPerature Mode selector

0: TW1 / TSD1 / TSD2 are active

1: TW1 / TW2 / TSD2 are active

[4] ICMP: VDD load current monitoring in VDD Standby Mode

0: monitoring enabled. The watchdog is disabled in VDD Standby Mode only if IVDD < ICMP

1: monitoring disabled. The watchdog is always disabled in VDD Standby mode

[3] VDD_VTH: VDD undervoltage monitoring reset threshold

0: low threshold selected

1: high threshold selected

[2] STBYSEL: STandBY SELect

0: VBAT Standby mode

1: VDD Standby mode

[1] GOSTBY: Go to Standby

0: no action

1: go-to-standby command (this bit is automatically cleared upon state transition).

[0] WDTRIG: WatchDog TRIGger Bit

Watchdog trigger bit (for a detailed description, please refer to Section 2.4).

L99ASC03 数据表(PDF) 54 Page - STMicroelectronics

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