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ADE7166 数据表(PDF) 130 Page - Analog Devices |
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ADE7166 数据表(HTML) 130 Page - Analog Devices |
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130 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 130 of 144 Table 141. SPI Configuration SFR 2 (SPIMOD2, 0xE9) Bit Mnemonic Default Description Master Mode, SPI Continuous Transfer Mode Enable Bit. SPICONT Result 0 The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can be initiated after a stalled period. 7 SPICONT 0 1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty. SPI Interface Enable Bit. SPIEN Result 0 The SPI interface is disabled. 6 SPIEN 0 1 The SPI interface is enabled. SPI Open-Drain Output Configuration Bit. SPIODO Result 0 Internal pull-up resistors are connected to the SPI outputs. 5 SPIODO 0 1 The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should not exceed the specified operating voltage. SPI Master Mode Enable Bit. SPIMS_b Result 0 The SPI interface is defined as a slave. 4 SPIMS_b 0 1 The SPI interface is defined as a master. SPI Clock Polarity Configuration Bit (see Figure 110). SPICPOL Result 0 The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit, the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is sampled on the rising or falling edge of SCLK. 3 SPICPOL 0 1 The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data input is sampled on the falling or rising edge of SCLK. SPI Clock Phase Configuration Bit (see Figure 110). SPICPHA Result 0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then every two subsequent edges. 2 SPICPHA 0 1 The SPI data output changes state at the first edge of SCLK and then every two subsequent edges, whereas the SPI data input is sampled at the second SCLK edge and then every two subsequent edges. Master Mode, LSB First Configuration Bit. SPILSBF Result 0 The MSB of the SPI outputs is transmitted first. 1 SPILSBF 0 1 The LSB of the SPI outputs is transmitted first. Transfer and Interrupt Mode of the SPI Interface. TIMODE Result 0 TIMODE 1 1 This bit must be left set for proper operation. |
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