ADE7166 datasheet(133/144 Pages) AD

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ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 133 of 144

SPI INTERRUPT AND STATUS FLAGS

The SPI interface has several status flags that indicate the status

of the double-buffered receive and transmit registers. Figure 109

shows when the status and interrupt flags are raised. The transmit

interrupt occurs when the transmit shift register is loaded with

the data in the SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)

SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A) register has not

been written with new data by the beginning of the next byte

transfer, the transmit operation stops.

When a new byte of data is received in the SPI/I2C Receive

Buffer SFR (SPI2CRx, 0x9B) register, the SPI receive interrupt

flag is raised. If the data in the SPI/I2C Receive Buffer SFR

(SPI2CRx, 0x9B) register is not read before new data is ready to

be loaded into the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B),

an overflow condition has occurred. This overflow condition,

indicated by the SPIRxOF flag, forces the new data to be discarded

or overwritten if the RxOFW bit is set.

SPITx

TRANSMIT SHIFT REGISTER

SPITxIRQ = 1

SPITx (EMPTY)

TRANSMIT SHIFT REGISTER

STOPS TRANSFER IF TIMODE = 1

SPIRx

RECEIVE SHIFT REGISTER

SPIRxIRQ = 1

SPIRx (FULL)

RECEIVE SHIFT REGISTER

SPIRxOF = 1

Figure 109. SPI Receive and Transmit Interrupt and Status Flags

SCLK

(SPICPOL=0)

MISO

SCLK

(SPICPOL = 1)

MOSI

SPIRx1 AND

SPITx1 FLAGS

SS_b

SPIRx0 AND

SPITx0 FLAGS

SPICPHA = 1

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MISO

MOSI

SPIRx1 AND

SPITx1 FLAGS

SPIRx0 AND

SPITx0 FLAGS

SPICPHA = 0

Figure 110. SPI Timing Configurations

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