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STM32F101X6 数据表(PDF) 14 Page - STMicroelectronics |
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STM32F101X6 数据表(HTML) 14 Page - STMicroelectronics |
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14 / 74 page  Description STM32F101xx 14/74 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Figure 1. STM32F101xx access line block diagram 1. AF = alternate function on I/O port pin. 2. TA = –40 °C to +85 °C (junction temperature up to 125 °C). Temp sen so r PA[ 15:0] EXTI W W D G NVIC 12bit ADC1 SWD 16AF JTDI JTCK/SWCLK JTMS/SWDIO JNTRST JTDO NRST VDD = 2 to 3.6V 80AF PB[ 15:0] PC[15:0] AHB2 MOSI,MISO,SCK,NSS SRAM 2x(8x16bit) WAKEUP GPIOA GPIOB GPIOC Fmax: 36 MHz VSS SCL,SDA I2C2 VREF+ GP DMA TIM2 TIM3 XTAL OSC 4-16 MHz XTAL 32 kHz OSC_IN OSC_OUT OSC32_OUT OSC32_IN PLL & PCLK1 HCLK CLOCK MANAGT PCLK 2 as AF as AF VOLT. REG. 3.3V TO 1.8V POWER Backu p i nterf ace as AF 16 KB RTC RC 8 MHz Cortex M3 CPU USART1 USART2 SPI2 7 channels Back up reg SCL,SDA,SMBA L I2C1 as AF RX,TX, CTS, RTS, USART3 VREF- PD[15:0] GPIOD 4 Chann els 4 Chann els FCLK RC 42 kHz Stand by IWDG @VDD @VBAT POR / PDR SUPPLY @VDDA VDDA VSSA @VDDA VBAT CK, SmartCard as AF RX,TX, CTS, RTS, Smart Card as AF RX,TX, CTS, RTS, NVIC SPI1 MOSI,MISO, SCK,NSS as AF IF in terface @VDDA SUPERVISION PVD Rst Int @VDD AHB2 APB2 APB 1 AWU TAMPER-RTC PE[15:0] GPIOE Flash 128 KB 64 bit Ibus Dbus pbus Trace Cont rol ler Syst em TIM4 4 Channels ai14385B TRACECLK TRACED[0:3] as AS SW/JTAG TPIU Trace/trig CK, SmartCard as AF |
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