STM32F101X6 datasheet(48/74 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F101xx

48/74

5.3.12

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 33 are derived from tests

performed under the conditions summarized in Table 7. All I/Os are CMOS and TTL

compliant.

Table 32.

Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = +105 °C conforming to JESD78A

II level A

Table 33.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(1)

Values based on characterization results, and not tested in production.

TTL ports

–0.5

0.8

VIH

Standard IO input high level

voltage(1)

2VDD+0.5

IO FT(2) input high level

voltage(1)

FT = Five-volt tolerant.

25.5V

VIL

Input low level voltage(1)

CMOS ports

–0.5

0.35 VDD

VIH

Input high level voltage(1)

0.65 VDD

VDD+0.5

Vhys

Standard IO Schmitt trigger

voltage hysteresis(3)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

200

IO FT Schmitt trigger voltage

hysteresis(3)

5% VDD

(4)

Ilkg

Input leakage current (4)

With a minimum of 100 mV.

VSS ≤VIN ≤VDD

Standard I/Os

±1

µA

VIN = 5 V

I/O FT

RPU

Weak pull-up equivalent

resistor(5)

Leakage could be higher than max. if negative current is injected on adjacent pins.

VIN = VSS

Ω

RPD

Weak pull-down equivalent

resistor(6)

Pull-up and pull-down resistors are designed with a true resistance in series with a switchable

PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order)

VIN = VDD

Ω

CIO

I/O pin capacitance

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