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STM32F101X6 数据表(PDF) 22 Page - STMicroelectronics |
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STM32F101X6 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 74 page ![]() Pin descriptions STM32F101xx 22/74 - - 85 - PD4 I/O FT PD4 USART2_RTS - - 86 - PD5 I/O FT PD5 USART2_TX - - 87 - PD6 I/O FT PD6 USART2_RX - - 88 - PD7 I/O FT PD7 USART2_CK 39 55 89 30 PB3/JTDO I/O FT JTDO PB3/TRACESWO TIM2_CH2 / SPI1_SCK 40 56 90 31 PB4/JNTRST I/O FT JNTRST PB4 TIM3_CH1 / SPI1_MISO 41 57 91 32 PB5 I/O PB5 I2C1_SMBAl TIM3_CH2 / SPI1_MOSI 42 58 92 33 PB6 I/O FT PB6 I2C1_SCL(8)/ TIM4_CH1(6) (8) USART1_TX 43 59 93 34 PB7 I/O FT PB7 I2C1_SDA(8)/ TIM4_CH2(6) (8) USART1_RX 44 60 94 35 BOOT0 I BOOT0 45 61 95 - PB8 I/O FT PB8 TIM4_CH3(6) (8) I2C1_SCL 46 62 96 - PB9 I/O FT PB9 TIM4_CH4(6) (8) I2C1_SDA - - 97 - PE0 I/O FT PE0 TIM4_ETR(6) - - 98 - PE1 I/O FT PE1 47 63 99 36 VSS_3 SVSS_3 48 64 100 1 VDD_3 SVDD_3 1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 8. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 6. Available only on devices with a Flash memory density equal or higher than 64 Kbytes. 7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. Table 3. Pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions(3) Default Remap |
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