ST7L09 datasheet(65/104 Pages) STMICROELECTRONICS

65 / 104 page

ST7L05, ST7L09

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8-BIT A/D CONVERTER (ADC) (Cont’d)

11.4.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = EOC Conversion Complete

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete

1: Conversion can be read from the DR register

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software. It is used

together with the SLOW bit to configure the ADC

clock speed. Refer to the table in the SLOW bit de-

scription.

Bit 5 = ADON A/D Converter On

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bit 4:3 = Reserved. must always be cleared.

Bits 2:0 = CH[2:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Notes:

1. The number of pins AND the channel selection varies

according to the device. Refer to the device pinout.

2. A write to the ADCCSR register (with ADON set) aborts

the current conversion, resets the EOC bit and starts a

new conversion.

DATA REGISTER (ADCDR)

Read Only

Reset Value: 0000 0000 (00h)

Bits 7:0 = D[7:0] Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

Note: Reading this register resets the EOC flag.

CONTROL/STATUS REGISTER 2 (ADCCSR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used

together with the SPEED bit to configure the ADC

clock speed as shown on the table below.

Bit 2:0 = Reserved. Forced by hardware to 0.

Note: If ADC settings are changed by writing the

ADCCSR2 register while the ADC is running, a

dummy conversion is needed before obtaining re-

sults with the new settings.

EOC

SPEED ADON

CH2

CH1

CH0

Channel Pin1)

CH2

CH1

CH0

AIN0

000

AIN1

001

AIN2

010

AIN3

011

AIN4

100

SLOW

fADC

SLOW SPEED

fCPU/2

fCPU

fCPU/4

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