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ST7L09 数据表(PDF) 97 Page - STMicroelectronics |
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ST7L09 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 104 page  ST7L05, ST7L09 97/104 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPTION BYTE 1 Bit 7 = Reserved, must always be 1 Bit 6 = PLLOFF PLL disabled 0: PLL enabled 1: PLL disabled (by-passed) Bit 5 = Reserved, must always be 1 Bit 4 = OSC RC Oscillator selection 0: RC oscillator on 1: RC oscillator off Note: If the RC oscillator is selected, then to im- prove clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. Table 23. List of Valid Option Combinations Note: See Clock Management Block diagram in Figure 12. Bits 3:2 = Reserved Bit 1 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Bit 0 = WDG HALT Watchdog Reset on Halt This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Operating conditions Option Bits VDD range Clock Source PLL Typ fCPU OSC PLLOFF 3.6 to 5.5V Internal RC 1% off 1 MHz @ 5V 0 1 x8 8 MHz @ 5V 0 External clock off 0 to 8 MHz 1 1 x8 8 MHz 0 OPTION BYTE 0 70 OPTION BYTE 1 70 Reserved SEC1 SEC0 FMP R FMP W Res. PLL OFF Res. OSC Res. Res. WDG SW WDG HALT Default Value 1 11111 0 011101111 1 |
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