ST7L09 datasheet(88/104 Pages) STMICROELECTRONICS

88 / 104 page

ST7L05, ST7L09

88/104

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40 to +105°C, unless otherwise specified

Notes:

1. Data based on characterization results, not tested in production.

2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 on page 74 and the

sum of IIO (I/O ports and control pins) must not exceed IVSS.

3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between

VILmax and VDD

4. To guarantee the reset of the device, a minimum pulse must be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

5. Guaranteed by design, not tested in production

Figure 64. RESET Pin Protection1)

Notes:

1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an

open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal

reset (watchdog).

- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 13.9.1 on page 88. Otherwise the reset will not be taken into account internally.

- Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in Section 13.2.2

on page 74.

2. Please refer to “Illegal Opcode Reset” on page 70 for more details on illegal opcode reset conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

VSS -0.3

0.3 x VDD

VIH

Input high level voltage

0.7 x VDD

VDD +0.3

Vhys

Schmitt trigger voltage

hysteresis1)

VOL

Output low level voltage

VDD =5V

IIO = +5mA

TA ≤ 85°C

TA ≤ 105°C

0.5

1.05)

1.25)

IIO = +2mA

TA ≤ 85°C

TA ≤ 105°C

0.2

0.45)

0.55)

RON

Pull-up equivalent resistor3)1)

VDD = 5V

Ω

tw(RSTL)ou

Generated reset pulse duration

Internal reset sources

µs

th(RSTL)in

External reset pulse hold time4)

tg(RSTL)in

Filtered glitch duration

200

0.01µF

EXTERNAL

RESET

CIRCUIT

USER

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE2)

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