ST7L09 datasheet(24/104 Pages) STMICROELECTRONICS

24 / 104 page

ST7L05, ST7L09

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SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)

7.3 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER

(MCCSR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO Main Clock Out enable

This bit is read/write by software and cleared by

hardware after a reset. This bit allows to enable

the MCO output clock.

0: MCO clock disabled, I/O port free for general

purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS Slow Mode select

This bit is read/write by software and cleared by

hardware after a reset. This bit selects the input

clock fOSC or fOSC/32.

0: Normal mode (fCPU = fOSC)

1: Slow mode (fCPU = fOSC/32)

RC CONTROL REGISTER (RCCR)

Read / Write

Reset Value: 1111 1111 (FFh)

Bits 7:0 = CR[7:0] RC Oscillator Frequency Ad-

justment Bits

These bits must be written immediately after reset

to adjust the RC oscillator frequency and to obtain

an accuracy of 1%. The application can store the

correct value for each voltage range in EEPROM

and write it to this register at start-up.

00h = maximum available frequency

FFh = lowest available frequency

Note: To tune the oscillator, write a series of differ-

ent values in the register until the correct frequen-

cy is reached. The fastest method is to use a di-

chotomy starting with 80h.

SYSTEM INTEGRITY (SI) CONTROL/STATUS

Read/Write

Reset Value: 0000 0x00 (0xh)

Bits 7:4 = Reserved, must be kept cleared.

Bit 3 = LOCKED PLL Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL reaches its operating fre-

quency.

0: PLL not locked

1: PLL locked

Bits 2:0 = Reserved, must be kept cleared.

Table 6. Clock Register Map and Reset Values

MCO

SMS

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

000

LOCK

Address

(Hex.)

Label

765

43210

0038h

MCCSR

Reset Value

000

MCO

SMS

0039h

RCCR

Reset Value

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

003Ah

SICSR

Reset Value

000

LOCKED

000

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