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ST7L09 数据表(PDF) 89 Page - STMicroelectronics |
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ST7L09 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 104 page  ST7L05, ST7L09 89/104 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.10.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC and TA, unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Figure 65. SPI Slave Timing Diagram with CPHA = 03) Notes: 1. Data based on design simulation and/or characterization results, not tested in production. 2. When no communication is on-going, the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. Symbol Parameter Conditions Min Max Unit fSCK =1/tc(SCK) SPI clock frequency Master (fCPU = 8 MHz) fCPU/128 = 0.0625 fCPU/4 = 2 MHz Slave (fCPU = 8 MHz) 0 fCPU/2 = 4 tr(SCK) tf(SCK) SPI clock rise and fall time see I/O port pin description tsu(SS) 1) SS setup time Slave 120 ns th(SS) 1) SS hold time tw(SCKH) 1) tw(SCKL) 1) SCK high and low time Master Slave 100 90 tsu(MI) 1) tsu(SI) 1) Data input setup time Master Slave 100 th(MI) 1) th(SI) 1) Data input hold time Master Slave 100 ta(SO) 1) Data output access time Slave 0 120 tdis(SO) 1) Data output disable time Slave 240 tv(SO) 1) Data output valid time Slave (after enable edge) 120 th(SO) 1) Data output hold time 0 tv(MO) 1) Data output valid time Master (after enable edge) 120 th(MO) 1) Data output hold time 0 SS INPUT CPHA = 0 MOSI INPUT MISO OUTPUT CPHA = 0 tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tv(SO) ta(SO) tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB IN LSB OUT Seenote2 CPOL = 0 CPOL = 1 tsu(SS) th(SS) tdis(SO) th(SO) See note 2 BIT1 IN 1 |
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