数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

RA4E2 数据表(PDF) 56 Page - Renesas Technology Corp

部件名 RA4E2
功能描述  Renesas Microcontrollers
PDF  91 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RA4E2 数据表(HTML) 56 Page - Renesas Technology Corp

Back Button RA4E2 Datasheet HTML 52Page - Renesas Technology Corp RA4E2 Datasheet HTML 53Page - Renesas Technology Corp RA4E2 Datasheet HTML 54Page - Renesas Technology Corp RA4E2 Datasheet HTML 55Page - Renesas Technology Corp RA4E2 Datasheet HTML 56Page - Renesas Technology Corp RA4E2 Datasheet HTML 57Page - Renesas Technology Corp RA4E2 Datasheet HTML 58Page - Renesas Technology Corp RA4E2 Datasheet HTML 59Page - Renesas Technology Corp RA4E2 Datasheet HTML 60Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 56 / 91 page
background image
Table 2.32
I3C timing (open drain timing parameters)
Conditions: VCC = 3.00 to 3.60 V
Setting of the I3C_SDA, I3C_SCL pins is not required with the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Max
Unit
Test
conditions
I3C
Open Drain
Timing
Parameters
SCL Clock Low Period
tLOW_OD
*1 *2
200
ns
Figure 2.45
tDIG_OD_L tLOW_ODmin + tfDA_ODmin —
ns
Figure 2.45
SCL Clock High Period
tHIGH*3 *4 —
41
ns
Figure 2.43
tDIG_H
tHIGH + tCF
ns
Figure 2.43
SDA Signal Fall Time
tfDA_OD
tCF
12
ns
Figure 2.45
SDA Data Setup Time Open
Drain Mode
tSU_OD*1
17
ns
Figure 2.44
Clock After START (S) Condition tCAS*5 *6 38.4 nano
For ENAS0: 1 µ
seconds
Figure 2.45
For ENAS1: 100
µ
For ENAS2: 2
milli
For ENAS3: 50
milli
Clock Before STOP (P)
Condition
tCBP
tCASmin / 2
seconds
Figure 2.46
Current Master to Secondary
Master Overlap time during
handoff
tMMOverla
p
tDIG_OD_Lmin
ns
Figure 2.51
Bus Available Condition
tAVAL*7
1
µs
Bus Idle Condition
tIDLE
1
ms
Time Internal Where New
Master Not Driving SDA Low
tMMLock
tAVALmin
µs
Figure 2.51
Note 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_Odmin.
Note 2. The Master may use a shorter Low period if it knows that this is safe, i.e., that SDA is already above VIH
Note 3. Based on tSPIKE, rise and fall times, and interconnect
Note 4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration
of the interconnect (e.g., a short Bus).
As a product specification, if this Max value cannot be guaranteed, change this Max value and specify that it cannot be used in the
Mixed Bus.
Note 5. On a legacy bus where I2C devices need to see Start
Note 6. Slaves that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3
Note 7. On a mixed bus with Fm Legacy I2C Devices, tAVAL is 300 ns shorter than the Fm Bus Free Condition time (tBUF)
RA4E2 Datasheet
2. Electrical Characteristics
R01DS0413EJ0150 Rev.1.50
May 29, 2026
Page 56 of 91



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com