ST10F268 datasheet(9/74 Pages) STMICROELECTRONICS

9 / 74 page

ST10F168

9/74

P1L.0 - P1L.7

P1H.0 - P1H.7

118-125

128-135

I/O

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the corresponding

output driver to high impedance state. Port1 is used as the 16-bit address bus (A) in

demultiplexed bus modes and also after switching from a demultiplexed bus mode

to a multiplexed bus mode.

The following Port1 pins have alternate functions:

132

P1H.4

CC24IO

CAPCOM2: CC24 Capture Input

133

P1H.5

CC25IO

CAPCOM2: CC25 Capture Input

134

P1H.6

CC26IO

CAPCOM2: CC26 Capture Input

135

P1H.7

CC27IO

CAPCOM2: CC27 Capture Input

XTAL1

138

XTAL1

Oscillator amplifier and internal clock generator input

XTAL2

137

XTAL2:

Oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2

unconnected. Minimum and maximum high / low and rise / fall times specified in the

AC Characteristics must be observed.

RSTIN

140

Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a speci-

fied duration while the oscillator is running resets the ST10F168. An internal pullup

resistor permits power-on reset using only a capacitor connected to VSS. In bidirec-

tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the

RSTIN line is pulled low for the duration of the internal reset sequence.

RSTOUT

141

Internal Reset Indication Output. This pin is set to a low level during hardware, soft-

ware or watchdog timer reset.

RSTOUT remains low until the EINIT (end of initial-

ization) instruction is executed.

NMI

142

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to

vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the

PWRDN (power down) instruction is executed, the NMI pin must be low in order to

force the ST10F168 to go into power down mode. If NMI is high and PWDCFG =’0’,

when PWRDN is executed, the part will continue to run in normal mode.

If it is not used, pin NMI should be pulled high externally.

VAREF

A/D converter reference voltage.

VAGND

A/D converter reference ground.

VPP/RPD

Flash programming voltage. Programming voltage of the on-chip Flash memory

must be supplied to this pin.

It is used also as the timing pin for the return from interruptible powerdown mode.

VDD

17,46,

56,72,

82,93,

109, 126,

136, 144

Digital Supply Voltage:

= + 5V during normal operation and idle mode.

> 2.5V during power down mode.

VSS

18,45,

55,71,

83,94,

110, 127,

139, 143

Digital Ground.

Table 1 : Pin Description (continued)

Symbol

Type

Function

ST10F268 数据表(PDF) 9 Page - STMicroelectronics

ST10F268 数据表(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

数据表下载