ST10F268 datasheet(56/74 Pages) STMICROELECTRONICS

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The real minimum value for TCL depends on the

jitter of the PLL. The PLL tunes fCPU to keep it

locked on fXTAL. The relative deviation of TCL is

the maximum when it is refered to one TCL

period. It decreases according to the formula and

to the Figure 19 given below. For

N periods of TCL

the minimum value is computed using the

corresponding deviation DN:

where N = number of consecutive TCL periods

and 1

≤ N ≤ 40. So for a period of 3 TCL periods

(N = 3):

= 4 - 3/15 = 3.8%

3TCLmin =3TCLNOM x (1 - 3.8/100)

=3TCLNOM x 0.962

3TCLmin = (57.72ns at fCPU = 25MHz)

This is especially important for bus cycles using wait

states and e.g. for the operation of timers, serial

interfaces, etc. For all slower operations and longer

periods (e.g. pulse train generation or measurement,

lower Baud rates, etc.) the deviation caused by the

PLL jitter is negligible (see Figure 19).

20.5.8 - External Clock Drive XTAL1

VDD = 5V ± 10%, VSS = 0V, for Q6 version : TA = -40, +85°C and for Q3 version TA = -40, + 125°C, unless

otherwise specified.

Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.

2. The input clock signal must reach the defined levels VIL and VIH2.

TCL

MIN

TCL

NOM

100

-------------

–







4N 15

) %

[]

⁄

–

(

Figure 19 : Approximated maximum PLL jitter

Symbol

Parameter

fCPU = fXTAL

fCPU = fXTAL / 2

fCPU = fXTAL x N

N = 1.5 / 2 / 2.5 / 3 / 4 / 5

Unit

Min.

Max.

Min.

Max.

Min.

Max.

tOSC

Oscillator period

40 1

1000

500

40 x N

100 x N

High time

18 2

–6 2

–10 2

–ns

Low time

18 2

–6 2

–10 2

–ns

Rise time

–

10 2

–6 3

–

10 2

Fall time

–

10 2

–6 2

–

10 2

Figure 20 : External clock drive XTAL1

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for

1 < N < 40 and 10MHz < fCPU < 25MHz.

VIH2

tOSC

VIL

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