ST10F268 datasheet(58/74 Pages) STMICROELECTRONICS

58 / 74 page

ST10F168

58/74

Note: 1. Partially tested, guaranteed by design characterization.

t23 CC Data hold after WR

26 + tF

–

2TCL - 14 + tF

–ns

t25 CC ALE rising edge after RD, WR

26 + tF

–

2TCL - 14 + tF

–ns

t27 CC Address / Unlatched CS hold

after RD, WR

26 + tF

–

2TCL - 14 + tF

–ns

t38 CC ALE falling edge to Latched CS

-4 - tA

10 - tA

-4 - tA

10 - tA

t39 SR Latched CS low to Valid Data In

–

40 + tC + 2tA

–

3TCL - 20

+ tC + 2tA

t40 CC Latched CS hold after RD, WR

46 + tF

–

3TCL - 14 + tF

–ns

t42 CC ALE fall. edge to RdCS, WrCS

(with RW delay)

16 + tA

–

TCL - 4 + tA

–ns

t43 CC ALE fall. edge to RdCS, WrCS

(no RW delay)

-4 + tA

–

-4 + tA

–ns

t44 CC Address float after RdCS, WrCS

(with RW delay)

–0

–

t45 CC Address float after RdCS, WrCS

(no RW delay)

–

TCL

t46 SR RdCS to Valid Data In (with RW

delay)

–16 + tC

–

2TCL - 24 + tC

t47 SR RdCS to Valid Data In (no RW

delay)

–36 + tC

–

3TCL - 24 + tC

t48 CC RdCS, WrCS Low Time (with RW

delay)

30 + tC

–

2TCL - 10 + tC

–ns

t49 CC RdCS, WrCS Low Time (no RW

delay)

50 + tC

–

3TCL - 10 + tC

–ns

t50 CC Data valid to WrCS

26 + tC

–

2TCL - 14+ tC

–ns

t51 SR Data hold after RdCS

0–

–

t52 SR Data float after RdCS

–20 + tF

–

2TCL - 20 + tF

t54 CC Address hold after RdCS, WrCS

20 + tF

–

2TCL - 20 + tF

–ns

t56 CC Data hold after WrCS

20 + tF

–

2TCL - 20 + tF

–ns

Table 24 : Multiplexed bus characteristics (continued)

Symbol

Parameter

Maximum CPU Clock

25MHz

Variable CPU Clock

1/2 TCL = 1 to 25MHz

Unit

Minimum

Maximum

Minimum

Maximum

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