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ST10F268 数据表(PDF) 41 Page - STMicroelectronics |
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ST10F268 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 74 page  ST10F168 41/74 The minimum reset circuit of Figure 14 is not ade- quate when the RSTIN pin is driven from the ST10F168 itself during software or watchdog trig- gered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above VIL after the end of the internal reset sequence, and thus will triggered an asynchronous reset sequence. Figure 14 shows an example of a reset circuit. In this example, R1C1 external circuit is only used to generate power-up or manual reset, and R0C0 circuit on VPP is used for power-up reset and to exit from powerdown mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets. R2 is an optional pullup for faster recovery and correct biasing of TTL Open Collector drivers. Figure 14 : System Reset Circuit RSTOUT VPP RSTIN VCC + C0 R0 ST10F168 External Hardware VCC R2 + C1 R1 D2 D1 o.d. External Reset Source Open Drain Inverter VCC |
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