ST10F268 datasheet(37/74 Pages) STMICROELECTRONICS

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ST10F168

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17 - SYSTEM RESET

System reset initializes the MCU in a predefined

state. There are five ways to activate a reset state.

The system start-up configuration is different for

each case as shown in Table 21.

17.1 - Asynchronous Reset (Long Hardware Reset)

An asynchronous reset is triggered when RSTIN

pin is pulled low while VPP pin is at low level. Then

the MCU is immediately forced in reset default

state. It pulls low RSTOUT pin, it cancels pending

internal hold states if any, it waits for any internal

access cycles to finish, it aborts external bus cycle,

it switches buses (data, address and control sig-

nals) and I/O pin drivers to high-impedance, it pulls

high Port0 pins and the reset sequence starts.

Power-on Reset

The asynchronous reset must be used during the

power-on of the MCU. Depending on crystal fre-

quency, the on-chip oscillator needs about 10ms

to 50ms to stabilize. The logic of the MCU does

not need a stabilized clock signal to detect an

asynchronous reset, so it is suitable for power-on

conditions. To ensure a proper reset sequence,

the RSTIN pin and the VPP pin must be held at low

level until the MCU clock signal is stabilized and

the system configuration value on Port0 is settled.

Hardware Reset

The asynchronous reset must be used to recover

from catastrophic situations of the application. It

may be triggerred by the hardware of the applica-

tion. Internal hardware logic and application cir-

cuitry are described in Reset circuitry chapter and

Figures 12, 13 and 14.

Exit of Asynchrounous Reset State

When the RSTIN pin is pulled high, the MCU

restarts. The system configuration is latched from

Port0 and ALE, RD and R/W pins are driven to their

inactive level. The MCU starts program execution

from memory location 00'0000h in code segment 0.

This starting location will typically point to the gen-

eral initialization routine. Timing of asynchronous

reset sequence are summarized in Figure 9.

Note: 1. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on

(fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).

Table 21 : Reset event definition

Reset Source

Short-cut

Conditions

Power-on reset

PONR

Power-on

Long Hardware reset (synchronous & asynchronous)

LHWR

t RSTIN > 1032 TCL

Short Hardware reset (synchronous reset)

SHWR

4 TCL < t RSTIN < 1032 TCL

Watchdog Timer reset

WDTR

WDT overflow

Software reset

SWR

SRST execution

Figure 9 : Asynchronous Reset Timing

6 or 8 TCL1

CPU Clock

RSTIN

Asynchronous

Reset Condition

VPP

RSTOUT

ALE

Port0

Reset Configuration

INST #1

Internal

Reset

Signal

Latching point of Port0

for system start-up

configuration

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