ST10F268 datasheet(25/74 Pages) STMICROELECTRONICS

25 / 74 page

ST10F168

25/74

Hardware traps are exceptions or error conditions

that arise during run-time. They cause immediate

non-maskable system reaction similar to a stan-

dard interrupt service (branching to a dedicated

vector table location).

The

occurrence

hardware

trap

additionally signified by an individual bit in the

trap flag register (TFR). Except when another

higher prioritized trap service is in progress, a

hardware trap will interrupt any other program

execution.

Hardware trap services cannot not be interrupted

by standard interrupt or by PEC interrupts.

Table 10 shows all of the possible exceptions or

error conditions that can arise during run-time :

Table 10 : Exceptions or error conditions that can arise during run-time

Exception Condition

Trap Flag Trap Vector

Vector Location

Trap Number

Trap Priority

Reset Functions

Hardware Reset

RESET

00’0000h

00h

III

Software Reset

RESET

00’0000h

00h

III

Watchdog Timer Overflow

RESET

00’0000h

00h

III

Class A Hardware Traps

Non-Maskable Interrupt

NMI

NMITRAP

00’0008h

02h

Stack Overflow

STKOF

STOTRAP

00’0010h

04h

Stack Underflow

STKUF

STUTRAP

00’0018h

06h

Class B Hardware Traps

Undefined Opcode

UNDOPC

BTRAP

00’0028h

0Ah

Protected Instruction Fault

PRTFLT

BTRAP

00’0028h

0Ah

Illegal Word Operand Access

ILLOPA

BTRAP

00’0028h

0Ah

Illegal Instruction Access

ILLINA

BTRAP

00’0028h

0Ah

Illegal External Bus Access

ILLBUS

BTRAP

00’0028h

0Ah

Reserved

[2Ch –3Ch]

[0Bh – 0Fh]

Software Traps

TRAP Instruction

Any [00’0000h– 00’01FCh]

in steps of 4h

Any [00h – 7Fh] Current CPU

Priority

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