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ST10F268 数据表(PDF) 57 Page - STMicroelectronics |
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ST10F268 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 74 page ![]() ST10F168 57/74 20.5.9 - Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and which represent the special characteristics of the programmed memory cycle. The following table describes how these variables are computed. 20.5.10 - Multiplexed Bus VDD = 5V ±10%, VSS = 0V, for Q6 version : TA = -40, +85°C and for Q3 version TA = -40, + 125°C, CL = 100pF, ALE cycle time = 6 TCL + 2tA + tC + tF (120ns at 25MHz CPU clock without wait states), unless otherwise specified. Symbol Description Values tA ALE Extension TCL x <ALECTL> tC Memory Cycle Time wait states 2TCL x (15 - <MCTC>) tF Memory Tristate Time 2TCL x (1 - <MTTC>) Table 24 : Multiplexed bus characteristics Symbol Parameter Maximum CPU Clock 25MHz Variable CPU Clock 1/2 TCL = 1 to 25MHz Unit Minimum Maximum Minimum Maximum t5 CC ALE high time 10 + tA – TCL - 10 + tA –ns t6 CC Address setup to ALE 4 + tA – TCL - 16+ tA –ns t7 CC Address hold after ALE 10 + tA – TCL - 10 + tA –ns t8 CC ALE falling edge to RD, WR (with RW-delay) 10 + tA – TCL - 10 + tA –ns t9 CC ALE falling edge to RD, WR (no RW-delay) -10 + tA – -10 + tA –ns t10 CC Address float after RD, WR 1 (with RW-delay) –6 – 6 ns t11 CC Address float after RD, WR 1 (no RW-delay) – 26 – TCL + 6 ns t12 CC RD, WR low time (with RW-delay) 30 + tC – 2TCL - 10 + tC –ns t13 CC RD, WR low time (no RW-delay) 50 + tC – 3TCL - 10 + tC –ns t14 SR RD to valid data in (with RW-delay) – 20 + tC – 2TCL - 20+ tC ns t15 SR RD to valid data in (no RW-delay) – 40 + tC – 3TCL - 20+ tC ns t16 SR ALE low to valid data in – 40 + tA + tC – 3TCL - 20 + tA + tC ns t17 SR Address / Unlatched CS to valid data in – 50 + 2tA + tC – 4TCL - 30 + 2tA + tC ns t18 SR Data hold after RD rising edge 0 – 0 – ns t19 SR Data float after RD 1 –26 + tF – 2TCL - 14 + tF ns t22 CC Data valid to WR 20 + tC – 2TCL - 20 + tC –ns |
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