ST10F268 datasheet(19/74 Pages) STMICROELECTRONICS

19 / 74 page

ST10F168

19/74

6 - CENTRAL PROCESSING UNIT (CPU)

The CPU includes a 4-stage instruction pipeline, a

16-bit arithmetic and logic unit (ALU) and dedi-

cated SFRs. Additional hardware has been added

for a separate multiply and divide unit, a bit-mask

generator and a barrel shifter.

Most of the ST10F168’s instructions can be exe-

cuted in one instruction cycle which requires

62.5ns at 32MHz CPU clock. For example, shift

and rotate instructions are processed in one

instruction cycle independent of the number of bit

to be shifted. Multiple-cycle instructions have

been optimized: branches are carried out in 2

cycles, 16 x 16-bit multiplication in 5 cycles and a

32/16 bit division in 10 cycles.The jump cache

reduces the execution time of repeatedly per-

formed jumps in a loop, from 2 cycles to 1 cycle.

The CPU uses a bank of 16 word registers to run

the current context. This bank of General Purpose

Registers (GPR) is physically stored within the

on-chip RAM area. A Context Pointer (CP) regis-

ter determines the base address of the active reg-

ister bank to be accessed by the CPU. The

number of register banks is only restricted by the

available internal RAM space. For easy parameter

passing, one register bank may overlap others.

A system stack of up to 2048 Byte stores tempo-

rary data. The system stack is allocated in the

on-chip RAM area, and it is accessed by the CPU

via the stack pointer (SP) register. Two separate

SFRs, STKOV and STKUN, are implicitly com-

pared against the stack pointer value on each

stack access, for the detection of a stack overflow

or underflow.

Figure 5 : CPU Block Diagram

Internal

RAM

2K Byte

General

Purpose

Registers

R15

MDH

MLD

Barrel-Shift

Mul./Div.-HW

Bit-Mask Gen.

ALU

16-Bit

STKOV

STKUN

Exec. Unit

Instr. Ptr

Instr. Reg

4-Stage

Pipeline

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Data Pg. Ptrs

Code Seg. Ptr.

CPU

256K Byte

Flash

memory

Bank

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