ST7261 datasheet(62/80 Pages) STMICROELECTRONICS

62 / 80 page

ST7261

62/80

11.8 I/O PORT PIN CHARACTERISTICS

11.8.1 General Characteristics

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production.

2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 43). Data based on design simulation and/or technology

characteristics, not tested in production.

3. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Figure 43. Two typical Applications with unused I/O Pin

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIL

Input low level voltage

0.3xVDD

VIH

Input high level voltage

0.7xVDD

VIN

Input voltage

True Open Drain I/O pins

VSS

6.0

Other I/O pins

VDD

Vhys

Schmitt trigger voltage hysteresis

400

Input leakage current

VSS≤VIN≤VDD

±1

µA

Static current consumption 2)

Floating input mode

200

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time

CL=50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time

tw(IT)in

External interrupt pulse time 3)

1tCPU

10k

Ω

UNUSED I/O PORT

ST72XXX

10k

Ω

UNUSED I/O PORT

ST72XXX

VDD

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