ST7261 datasheet(23/80 Pages) STMICROELECTRONICS

23 / 80 page

ST7261

23/80

POWER SAVING MODES (Cont’d)

7.3 HALT MODE

The HALT mode is the MCU lowest power con-

sumption mode. The HALT mode is entered by ex-

ecuting the HALT instruction. The internal oscilla-

tor is then turned off, causing all internal process-

ing to be stopped, including the operation of the

on-chip peripherals.

When entering HALT mode, the I bit in the Condi-

tion Code Register is cleared. Thus, any of the ex-

ternal interrupts (ITi or USB end suspend mode),

are allowed and if an interrupt occurs, the CPU

clock becomes active.

The MCU can exit HALT mode on reception of ei-

ther an external interrupt on ITi, an end suspend

mode interrupt coming from USB peripheral, or a

reset. The oscillator is then turned on and a stabi-

lization time is provided before releasing CPU op-

eration. The stabilization time is 514 CPU clock cy-

cles.

After the start up delay, the CPU continues opera-

tion by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

Figure 21. HALT Mode Flow Chart

EXTERNAL

INTERRUPT*

RESET

HALT INSTRUCTION

514 CPU CLOCK

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLES DELAY

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

SET

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

OFF

CLEARED

OFF

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

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