ST7261 datasheet(54/80 Pages) STMICROELECTRONICS

54 / 80 page

ST7261

54/80

11.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA.

11.5.1 General Timings

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch.

∆t

c(INST) is the number of tCPU cycles needed to finish

the current instruction execution.

11.5.2 CONTROL TIMING CHARACTERISTICS

Note 1:

Not tested in production, guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

tc(INST)

Instruction cycle time

fCPU=8MHz

tCPU

250

375

1500

tv(IT)

Interrupt reaction time 2)

tv(IT) = ∆tc(INST) + 10 tCPU

fCPU=8MHz

tCPU

1.25

2.75

µs

CONTROL TIMINGS

Symbol

Parameter

Conditions

Value

Unit

Min 1)

Typ. 1)

Max 1)

fOSC

Oscillator Frequency

MHz

fCPU

Operating Frequency

MHz

tRL

External RESET

Input pulse Width

1.5

tCPU

tPORL

Internal Power Reset Duration

514

tCPU

TRSTL

Reset Pin Output Pulse Width

µs

tWDG

Watchdog Time-out

fcpu = 8MHz

65536

8.192

4194304

524.288

tCPU

tOXOV

Crystal Oscillator

Start-up Time

tDDR

Power up rise time

from VDD = 0 to 4V

100

ST7261 数据表(PDF) 54 Page - STMicroelectronics

ST7261 数据表(HTML) 54 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载

链接网址

ST7261 数据表(PDF) 54 Page - STMicroelectronics

ST7261 数据表(HTML) 54 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表 下载

链接网址

数据表下载