ST7261 datasheet(37/80 Pages) STMICROELECTRONICS

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ST7261

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USB INTERFACE (Cont’d)

9.3.4 Register Description

DMA ADDRESS REGISTER (DMAR)

Read / Write

Reset Value: Undefined

Bits 7:0=DA[15:8]

DMA address bits 15-8.

Software must write the start address of the DMA

memory area whose most significant bits are given

by DA15-DA6. The remaining 6 address bits are

set by hardware. See the description of the IDR

INTERRUPT/DMA REGISTER (IDR)

Read / Write

Reset Value: xxxx 0000 (x0h)

Bits 7:6 = DA[7:6]

DMA address bits 7-6.

Software must reset these bits. See the descrip-

tion of the DMAR register and Figure 27.

Bits 5:4 = EP[1:0]

Endpoint number (read-only).

These bits identify the endpoint which required at-

tention.

00: Endpoint 0

01: Endpoint 1

10: Endpoint 2

When a CTR interrupt occurs (see register ISTR)

the software should read the EP bits to identify the

endpoint which has sent or received a packet.

Bits 3:0 = CNT[3:0]

Byte count (read only).

This field shows how many data bytes have been

received during the last data reception.

Note: Not valid for data transmission.

Figure 27. DMA Buffers

DA15

DA14

DA13

DA12

DA11

DA10

DA9

DA8

DA7

DA6

EP1

EP0

CNT3

CNT2

CNT1

CNT0

Endpoint 0 RX

Endpoint 0 TX

Endpoint 2 RX

Endpoint 1 TX

000000

000111

001000

001111

010000

010111

011000

011111

DA15-6,000000

Endpoint 1 RX

Endpoint 2 TX

100000

100111

101000

101111

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