ST7261 datasheet(40/80 Pages) STMICROELECTRONICS

40 / 80 page

ST7261

40/80

USB INTERFACE (Cont’d)

DEVICE ADDRESS REGISTER (DADDR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = Reserved. Forced by hardware to 0.

Bits 6:0 = ADD[6:0]

Device address, 7 bits.

Software must write into this register the address

sent by the host during enumeration.

Note: This register is also reset when a USB reset

is received from the USB bus or forced through bit

FRES in the CTLR register.

ENDPOINT n REGISTER A (EPnRA)

Read / Write

Reset Value: 0000 xxxx (0xh)

These registers (EP0RA, EP1RA and EP2RA) are

used for controlling data transmission. They are

also reset by the USB bus reset.

Note: Endpoint 2 and the EP2RA register are not

available on some devices (see device feature list

and register map).

Bit 7 = ST_OUT

Status out.

This bit is set by software to indicate that a status

out packet is expected: in this case, all nonzero

OUT data transfers on the endpoint are STALLed

instead of being ACKed. When ST_OUT is reset,

OUT transactions can have any number of bytes,

as needed.

Bit 6 = DTOG_TX

Data Toggle, for transmission

transfers.

It contains the required value of the toggle bit

(0=DATA0, 1=DATA1) for the next transmitted

data packet. This bit is set by hardware at the re-

ception of a SETUP PID. DTOG_TX toggles only

when the transmitter has received the ACK signal

from

the

USB

host.

DTOG_TX

and

also

DTOG_RX (see EPnRB) are normally updated by

hardware, at the receipt of a relevant PID. They

can be also written by software.

Bits 5:4 = STAT_TX[1:0]

Status bits, for transmis-

sion transfers.

These bits contain the information about the end-

point status, which are listed below:

These bits are written by software. Hardware sets

the STAT_TX bits to NAK when a correct transfer

has occurred (CTR=1) related to a IN or SETUP

transaction addressed to this endpoint; this allows

the software to prepare the next set of data to be

transmitted.

Bits 3:0 = TBC[3:0]

Transmit byte count for End-

point n.

Before transmission, after filling the transmit buff-

er, software must write in the TBC field the trans-

mit packet size expressed in bytes (in the range 0-

8).

Warning: Any value outside the range 0-8 will-

induce undesired effects (such as continuous data

transmission).

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

ST_

OUT

DTOG

_TX

STAT

_TX1

STAT

_TX0

TBC

STAT_TX1 STAT_TX0 Meaning

DISABLED: transmission

transfers cannot be executed.

STALL: the endpoint is stalled

and all transmission requests

result in a STALL handshake.

NAK: the endpoint is naked

and all transmission requests

result in a NAK handshake.

VALID: this endpoint is ena-

bled for transmission.

ST7261 数据表(PDF) 40 Page - STMicroelectronics

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