ST7261 datasheet(39/80 Pages) STMICROELECTRONICS

39 / 80 page

ST7261

39/80

USB INTERFACE (Cont’d)

Bit 3 = IOVR

Interrupt overrun.

This bit is set when hardware tries to set ERR, or

SOF before they have been cleared by software.

0: No overrun detected

1: Overrun detected

Bit 2 = ESUSP

End suspend mode.

This bit is set by hardware when, during suspend

mode, activity is detected that wakes the USB in-

terface up from suspend mode.

This interrupt is serviced by a specific vector, in or-

der to wake up the ST7 from HALT mode.

0: No End Suspend detected

1: End Suspend detected

Bit 1 = RESET

USB reset.

This bit is set by hardware when the USB reset se-

quence is detected on the bus.

0: No USB reset signal detected

1: USB reset signal detected

Note: The DADDR, EP0RA, EP0RB, EP1RA,

EP1RB, EP2RA and EP2RB registers are reset by

a USB reset.

Bit 0 = SOF

Start of frame.

This bit is set by hardware when a low-speed SOF

indication (keep-alive strobe) is seen on the USB

bus. It is also issued at the end of a resume se-

quence.

0: No SOF signal detected

1: SOF signal detected

Note: To avoid spurious clearing of some bits, it is

recommended to clear them using a load instruc-

tion where all bits which must not be altered are

set, and all bits to be cleared are reset. Avoid read-

modify-write instructions like AND , XOR..

INTERRUPT MASK REGISTER (IMR)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:0 = These bits are mask bits for all interrupt

condition bits included in the ISTR. Whenever one

of the IMR bits is set, if the corresponding ISTR bit

is set, and the I bit in the CC register is cleared, an

interrupt request is generated. For an explanation

of each bit, please refer to the corresponding bit

description in ISTR.

CONTROL REGISTER (CTLR)

Read / Write

Reset Value: 0000 0110 (06h)

Bits 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = RESUME

Resume.

This bit is set by software to wake-up the Host

when the ST7 is in suspend mode.

0: Resume signal not forced

1: Resume signal forced on the USB bus.

Software should clear this bit after the appropriate

delay.

Bit 2 = PDWN

Power down.

This bit is set by software to turn off the 3.3V on-

chip voltage regulator that supplies the external

pull-up resistor and the transceiver.

0: Voltage regulator on

1: Voltage regulator off

Note: After turning on the voltage regulator, soft-

ware should allow at least 3 µs for stabilisation of

the power supply before using the USB interface.

Bit 1 = FSUSP

Force suspend mode.

This bit is set by software to enter Suspend mode.

The ST7 should also be halted allowing at least

600 ns before issuing the HALT instruction.

0: Suspend mode inactive

1: Suspend mode active

When the hardware detects USB activity, it resets

this bit (it can also be reset by software).

Bit 0 = FRES

Force reset.

This bit is set by software to force a reset of the

USB interface, just as if a RESET sequence came

from the USB.

0: Reset not forced

1: USB interface reset forced.

The USB is held in RESET state until software

clears this bit, at which point a “USB-RESET” in-

terrupt will be generated if enabled.

SUS

DOV

CTR

ERR

IOVR

ESU

SPM

RES

ETM

SOF

RESUME

PDWN

FSUSP

FRES

ST7261 数据表(PDF) 39 Page - STMicroelectronics

ST7261 数据表(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载