ST7261 datasheet(65/80 Pages) STMICROELECTRONICS

65 / 80 page

ST7261

65/80

I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 51. Typical VDD-VOH vs. VDD (high sink port)

11.9 CONTROL PIN CHARACTERISTICS

11.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPÜ, and TA unless otherwise specified.

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production.

2. Data based on characterization results, not tested in production.

3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

4. The IIO current sunk must always respect the absolute maximum rating specified in Section 11.2 and the sum of IIO (I/

O ports and control pins) must not exceed IVSS.

5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 52). This data is based on characterization results, not tested in production.

6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

0.02

0.04

0.06

0.08

0.1

33.544.5

5.5

Vdd(V)

0.05

0.1

0.15

0.2

0.25

Vdd(V)

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIH

Input High Level Voltage

0.7xVDD

VDD

VIL

Input Low Voltage

VSS

0.3xVDD

Vhys

Schmitt trigger voltage hysteresis 3)

400

VOL

Output low level voltage 4)

(see Figure 53, Figure 54)

VDD=5V

IIO=5mA

IIO=2mA

0.4

RON

Weak pull-up equivalent resistor 5)

VIN=VSS

160

280

Ω

tw(RSTL)out Generated reset pulse duration

External pin or

internal reset sources

1/fSFOSC

µs

th(RSTL)in External reset pulse hold time

µs

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