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ST92141 数据表(PDF) 123 Page - STMicroelectronics |
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ST92141 数据表(HTML) 123 Page - STMicroelectronics |
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123 / 179 page  123/179 ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC) INDUCTION MOTOR CONTROLLER (Cont’d) 7.4.5.2 IMC Software Operating mode In this operating mode, the Repetition register and any Compare register can be independently up- dated by software by setting the SDT bit in the PCR2 register (this bit will be reset by hardware) and the corresponding enable bit in the same reg- ister. No hardware loading is performed when an ADT interrupt is generated. Note: The Repetition Counter is decremented im- mediately when the Repetition Counter is updated. 7.4.6 IMC Output selection The IMC Output can be selected from the following sources: – OPR register (bit 5:0), by setting the ODS bit in the OPR register. – Dead Time Generator outputs, by setting the ODCS bit in PCR0 register. – PWM Counter outputs (h and l) are not comple- mented when the ODCS bit is reset. Figure 70 shows the IMC output selection. Figure 70. IMC Output selection. 0 1 0 1 UH UL VH VL WH WL PWM Counter Dead Time ODS bit ODCS bit Generator OPR Register PSR Register 9 |
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