数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ST92141 数据表(PDF) 133 Page - STMicroelectronics

部件名 ST92141
功能描述  8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL
PDF  179 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST92141 数据表(HTML) 133 Page - STMicroelectronics

Back Button ST92141 Datasheet HTML 129Page - STMicroelectronics ST92141 Datasheet HTML 130Page - STMicroelectronics ST92141 Datasheet HTML 131Page - STMicroelectronics ST92141 Datasheet HTML 132Page - STMicroelectronics ST92141 Datasheet HTML 133Page - STMicroelectronics ST92141 Datasheet HTML 134Page - STMicroelectronics ST92141 Datasheet HTML 135Page - STMicroelectronics ST92141 Datasheet HTML 136Page - STMicroelectronics ST92141 Datasheet HTML 137Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 133 / 179 page
background image
133/179
ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
DEAD TIME GENERATOR REGISTER (DTG)
R254 - Read/Write
Register Page: 48
Reset Value: 0011 1111 (3Fh)
Bit 7:6 = Reserved.
Bit 5:0 = DTG[5:0]
Dead time generator value (N).
The delay is N x INTCLK period multiplied by 2.
If N = 0 the delay is 0.
IMC INTERRUPT VECTOR REGISTER (IMCIVR)
R255 - Read/Write
Register Page: 48
Reset Value: undefined (17h)
Bit 7:4 = V[3:0]:
Interrupt Vector Base Address.
User programmable interrupt vector bits.
The most significant nibble of the interrupt vector
address is given by V[3:0]. The other nibble is giv-
en by W[3:0] where W[0] is forced to ‘0’ and W[3:1]
are set by hardware according to the Table 26 In-
terrupt Source Address.
Table 26. Interrupt Source Address
Bit 3 = NMI:
Non Maskable Interrupt pending bit.
This bit is set by hardware when an NMI event oc-
curs and the NMIE bit = 1. The NMI bit can be
cleared by software. It cannot be set by software.
As long as this bit is ‘1’ the NMI signal to ST9 is
kept active (high level).
0: No NMI pending
1: NMI pending
Note: As long as the external NMI signal is active
the NMI bit can not be reset.
Bit 2:0 = PL[2:0]: Priority level for the peripheral
interrupt.
70
-
-
DTG5 DTG4 DTG3 DTG2 DTG1 DTG0
70
V3
V2
V1
V0
NMI
PL2
PL1
PL0
W[3:1]
Interrupt Source
000
ADT Data transfer
001
ZPC Zero event of PWM counter
010
CM0 PWM counter Compare 0
011
CPT Tacho capture
100
CPU Compare U
101
CPV Compare V
110
CPW Compare W
111
OTC Tacho counter overflow
9



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com