STLC5432 datasheet(8/46 Pages) STMICROELECTRONICS

8 / 46 page

INTRODUCTION

This single chip CMOS Device interfaces the

physical multiplex of the application to the physi-

cal CEPT transmission link at 2048kb/s.

STLC5432 contains analog and digital functions

to implement line interface function and frame

synchronization. It meets pulse shape and jitter

specifications in accordance with CCITT Recom-

mendations and CEPT standards.

FUNCTIONAL DESCRIPTION

1. LINE INTERFACE

1.1 Receiver

The receive input signal should be derived via a

transformer of the same type used for the trans-

mit direction. The suggested transformer is the

VAC L4097-X004 or equivalent for the 75 ohms

case and the VAC 4097-X012 or equivalent for

the 120 ohms case. The electrical models of the

transformers are summarized in the following ta-

ble :

Loads

(

Ω)

(

µH)

(pF)

(mH)

Rcul

(

Ω)

Rculll

(

Ω)

1.57:1:1

≤0.3

≤15

≥2

0.11

0.23

120

2:1:1

≤0.2

≤15

≥2

0.10

0.20

with:

Winding ratioes

Ls:

Leakage inductance

Ck:

Inter winding capacitance

Lh:

Principal inductance of

windings

RcuI and RcuIII :

DC resistances of

winding I and III.

Wiring between the transformer and the circuit

should respect the application schematic given in

annex. (see fig 4).

The internal fixed threshold is set to 200 mV over

the common mode voltage VCM (VCM = 2.375 V

nominal) to insure the specified transmission

range with a good noise immunity.

Two options are provided for special applications

requiring improved transmission ranges:

AUTO-ADAPTATIVE THRESHOLD:

Using the configuration register CR4 (AVT), a

peak amplitude detector circuit is connected to

the received signal and after digital processing,

an adaptative threshold value equal to 3/8 of

the peak value is obtained at the output of a D

to A converter and used for data detection.

AUTOMATIC EQUALIZER: connecting two ex-

ternal capacitors of 100pF in series between the

transformer and the circuits inputs, and using the

configuration register CR4 (EQV), the circuit will

select automatically a pre-compensation filter for

long line configuration (see application sche-

matic on figure 3 and 4 given in annex).

64KHz

CLOCK

BIN/HDB3

ENCODER

BXDI

BXDO

RD RX

D93TL045B

SELEX

LP2

SIG

CRC4

LP4

DOUT

RDS

2n-1

GENERATOR

TSO

GENERATOR

SIG

SGV

DIN

ADAPTOR: WHEN

DATA IN CLOCK IS AT

64KHz, DATA OUT

CLOCK AT 2048KHz

BXDI

Figure 2: Transmitter Diagram

STLC5432

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