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STLC5432 数据表(PDF) 40 Page - STMicroelectronics |
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STLC5432 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 46 page ![]() ts LCLK LFSX LFSR tH ts DIN DCP = 0 D93TL066A BIT n T tH DOUT tpd tpdz SINGLE PULSE T = 488ns MULTIPLEX AT 2Mb/s T = 244ns MULTIPLEX AT 4Mb/s T = 122ns MULTIPLEX AT 8Mb/s DEL = 0 NOT DELAYED MODE BIT n IS THE FIRST BIT OF THE FRAME (125 µs) BIT 0 TIME SLOT ZERO (LIKE GCI) DEL = 1 DELAYED MODE BIT n IS THE LAST BIT OF THE FRAME (125 µs) Figure 20: Single Clock Delayed Mode. 3.9 µs LCLK DOUT 0 DOUT 1 DOUT 2 DOUT 3 EX: FOUR ST5432 OUTPUTS WHEN CONNECTED TO THE SAME MULTIPLEX AT 8Mb/s D93TL067 Figure 21: Multiplex Diagram STLC5432 40/46 |
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