STLC5432 datasheet(11/46 Pages) STMICROELECTRONICS

11 / 46 page

5.3.1 Typical case

Remote entity transmits Frame Alignment Signal

(FAS) and Multiframe Alignment Signal (MFAS).

As soon as lost of Frame Alignment is occured

(LOF = 1), the local receiver recovers FAS from

254 up to 500

µs after. As soon as FAS is recov-

ered (LOF = 0), the local receiver recovers MFAS

from 4 up to 6ms after.

5.3.2 Old Existing Equipment Case

Remote entity transmits Frame Alignment Signal

(FAS) without Multiframe Alignment Signal (MFAS).

As soon as lost of Frame Alignment is occured

(LOF=1), the local receiver recovers FAS from 254

up to 500

µs after. Then LOF = 0, and 400ms after

the local receiver indicates that the Multiframe Aligne-

ment Signal has not been recovered (MFNR = 1).

5.3.3 Particular Case: Spurious Frame Alignment

Signal

Local receiver receives true FAS and true MFAS

among several spurious FAS.

Multiframe Alignment signal (MFR=1) is recovered

from 8 to 400ms after the Frame Alignment signal

is recovered (LOF=0). Then, this FAS is either a

spurious one (the ”Spurious Time slot Zero” is car-

rying FAS without MFAS), or true FAS.

Anyway, when the Multiframe Alignment has been

recovered (MFR=1), the good Frame Alignment

Signal is taken into account and data are loaded

into the Frame Memory at the good location.

See Fig. 13 synchronization algorithm.

5.3.4 Worst Case

Local receiver receives true FAS and true MFAS

among several spurious FAS and several spuri-

ous MFAS.

In this case, if the circuit has recovered a spuri-

ous FAS and MFAS, the CRC blocks will be de-

tected with an high error rate. As soon as 915 er-

rored CRC block within 1000 will be detcted, the

MFAS will be assumed as spurious and a new re-

search starts at the point just after the location of

the assumed spurious Frame Alignement Signal.

5.4 Transmitter SIDE

The Frame Alignement Signal is transmitted con-

tinuously on the transmitter side, with bit 1 of TS0

at logical 1. The MFAS signal is transmitted in ac-

cordance with NMF bit register (CR5 Register): if

NMF is programmed to ”1” Logic, no MFAS is

transmitted; if NMF is programmed to ”0” Logic

the MFAS signal is transmitted continuously.

Table 2.

LOF

MFR

MFNR

RECEIVER STATE

FAS or MFAS has been lost.

State: Research of FAS

FAS has been recovered.

State: Research of MFAS

Frame and Multiframe recovered

State: Good working.

Frame recovered.

State: Good working without

multiframe received from

transmitting side.

6 Interfacing with the microprocessor

The device can work in one of the 3 following

modes :

– Parallel microprocessor Interface Mode

– Serial microprocessor Interface Mode

– Without microprocessor : Stand Alone Mode.

The choice is done by means of the SA/Reset, P0

and P1 pins.

6.1 Parallel Microprocessor Interface Mode

The microprocessor can read (or write) the regis-

ters of the STLC5432 using the fifteen parallel In-

terface pins.

The use of TSO (Time Slot Zero) of DIN and

DOUT digital multiplex is defined by TSOE bit of

CR5 Register.

– If TSOE = 1, TSO on DIN multiplex Input is

used to transfer Sa4 to Sa8 bits to the line

and TSO on DOUT multiplex output is used to

transfer Sa4 to Sa8 bits from the line.

– If TSOE = 0, DOUT output is high impedance

during TSO, and DIN Input ignores data dur-

ing TSO.

6.2 Serial Microprocessor Interface Mode

Fifteen parallel Interface pins are ignored, they

are tied to ground. In this mode, the time slots 0

of internal multiplexes are considered like a chan-

nel used by the devices and the control entity lo-

cated in the system to communicate. This chan-

nel can be switched across a switching network

-or not- before its final destination.

The message is constituted by two bytes which

are transmitted on two consecutive Time Slots

Zero.

The bits of word are numbered 0 to 7, bit 0 is

transmitted first. When the bit 7 of a byte is 0, this

byte is the first word of the message.

The bit 6, of the first word, is R/W bit:

R/W = 1. Message to read a register whose ad-

dress is designated by the following bits of the

word ( A 0/5).

STLC5432

11/46

STLC5432 数据表(PDF) 11 Page - STMicroelectronics

STLC5432 数据表(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表下载