STLC5432 datasheet(12/46 Pages) STMICROELECTRONICS

12 / 46 page

R/W = 0. Message to write a register, addressed

by the bits A0/5.

The bit 7 of following byte is 1 and the seven

D 0/6 bits are data to load into register.

To transfer one message, 250

µs are necessary.

Between two messages, the bits are 1 during

TS0. See fig.7 for details.

6.2.1 Reading of a register

The remote entity connected to the DIN and

DOUT multiplexes can request reading of a regis-

ter if it transmits, during TSO, on DIN the address

bit A0/5, the R/W bit at 1 and the last bit at 0. The

following word, ending with 1, is not taken into ac-

count by the device. The device returns two

words during TSO of DOUT :

–The first word begins with 0, R/W bit is put to

1, the address bits of the register are trans-

mitted.

–The second word begins with 1, then seven

data bits of the register are transmitted.

6.2.2 Writing of a register

The remote entity connected to the DIN and

DOUT multiplexes can request writing, then it

transmits the first bit at 0, the second bit at 0 and

the register address A 0/5 during TSO of DIN.

The following word begins with 1 and seven next

bits are Data to load into register. There is no ac-

knowledge after writing. The writing messages

can be transmitted consecutively.

6.3 Stand Alone Mode

Whatever the received frequency on LCLK pin

(2.048kHz or 4.096kHz), the device automatically

fits and always works at 2.048kHz. When SA pin

is at 1, the multiframe research is automatically

launched after each lost of frame and the device

provides the following alarms on DOUT during the

Time Slot 0:

F/S

SKIP

MFNR LOF

AIS

LOS

Loss of signal

AIS

Alarm Indication Signal

If LOF = 1, then B = 915

If LOF = 0, then B = WER

LOF

Loss of Frame

MFNR

Multi Frame Not Recovered

A Bit Received

SKIP

Jump

F/S

Fast/Slow.

Bits definitions are the same than bits definitions of

ALR, CAR1 and CAR2 Registers. These bits repre-

sent the current state of the line; DIN is ignored dur-

ing Time Slot Zero.

7 RESET

During Hardware Reset (Pin : SA/RESET) :

– All the programmable registers are configurated

with the default value.

– Interrupts are not generated (INT PIN is high

impedance).

– The research of Multiframe is always active.

At Software Reset (addressing the Reset register):

– The registers are configurated with the default

value only.

After Reset :

– The registers may be configurated with any

value.

8 INTERRUPT

All the bits of Alarm Registers generate an inter-

rupt if they are not masked, except SLC (CAR2).

An alarm generates an interrupt if the mask bit

associated is 0. If a temporary event is detected

from the line. ALR Alarm Register, CAR1 and

CAR2 Complementary Alarm Registers can be

read after interrupt or by polling.

In this last case, these Alarm Registers can be

considered like particular status registers.

If a temporary event is detected from the line,

then the appropriate bit is put to one. After read-

ing by the microprocessor, this bit is put to zero

until new event.

If a permanent state occurs, then the appropriate

bit is put to one. After reading by the microproces-

sor, this bit remains at one until disappearance of

the cause.

8.1 Parallel Interface Mode

ALR Alarm Register, CAR1 and CAR2 Comple-

mentary Alarm Registers can be read after inter-

rupt or by polling.

In this last case, these Alarm Registers can be

considered like particular status registers.

INT pin is put to 0 volt. The microprocessor reads

Alarm Register.

For example, after reading the ALR and CAR1

registers the microprocessor could act as follows:

– If SC bit (clock 1 second) is 1, then the micro-

processor reads fault counter registers.

– If EXT1 bit (EXTENSION 1) is 1, then the mi-

croprocessor reads Complementary Alarm

– If TSOR (or Sa6R) bit of CAR1 is 1, the mi-

croprocessor reads TSORR (or Sa6RR) Reg-

ister

STLC5432

12/46

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